Analysis and Implementation of OVSF Address Decoders

Demand for Internet of Things (IoT) devices has generated interest in fault-tolerant address decoders. Address decoders affect the energy required to establish a data link and monitor wireless channel through metrics such as detection probability false alarm probability. This brief establishes framework calculating probabilities shows that limiting number correctable errors eliminates simultaneous alarms, reduces alarm, maximum normalized power consumption sleep node due alarms by 16.9 dB. The expressions are formulated so probability, transmit, can be adjusted digitally, yielding counter-based implementation decoder 1.3 pJ/bit rate 200 bps $0.18~\mu \text{m}$ CMOS.